|
|
|
|
ECE 551 Digital System
Design and Synthesis |
Announcements:
Homework
#6 is posted below.
Instructor:
Michael G. Morrow, email:morrow@engr.wisc.edu
3441 Engineering Hall, 890-0805
Office Hours
TA:
Arslan Zulfiqar, email:
zulfiqar@wisc.edu
Office Hours: Thursday, 4:00-5:00pm, in B555 EH
Course
Materials:
Course Syllabus
Educational Objectives
Lecture Slides
Week 0/1 regfile_4 solution
Week 2
Week 3
Week 4
Week 5
Week 6 uart example solution
Week 7
Week 8
Week 9
Week 10
Week 11
Week 12
Week 13
Week 14
Week 15
Homework
Assignment #1
Solution
Assignment #2
Solution
Assignment #3
Solution
Assignment #4
Solution Recursive Average
Assignment #5
Solution
Assignment #6
Solution
Discussion Materials
Discussion #1 (ZIP)
Project Discussion (ZIP)
Exams
Midterm 1 Review Slides
Midterm 2
Project
Assignment
Tutorials
ModelSim
DesignView
External
Links:
http://www.verilog.com/
|
|
|
|